Hello, It's Me

Kosuru Karthik

And I'm a

Multidisciplinary professional with 3+ years in Web Design and VLSI Engineering.

More About Me

About Me

Kosuru Karthik – VLSI Engineer & Web Designer

M.Tech VLSI student at KL University with expertise in digital design, RISC-V, and low-power optimization.

3+ years in Web Design and Frontend Development, bridging hardware and user interfaces.

Name: Kosuru Karthik

Email: kosuru0062@gmail.com

Phone: +91 9398394847

Education: M.Tech VLSI

Experience: 3+ Years

Location: Vizag / Tenali

Download CV

My Skills

Web Design

HTML/CSS
95%

JavaScript
85%

React.js
75%

UI/UX
80%

VLSI & Hardware

Verilog / VHDL
90%

RISC-V
85%

Xilinx Vivado
88%

FPGA
80%

Tools

Git / GitHub
85%

Python
80%

MATLAB
75%

LaTeX
90%

My Projects

Low-Power RISC-V SoC

32-bit RISC-V processor with enable-based clock gating achieving 50% ALU power reduction.
Verilog | Vivado | Artix-7

Key Features

Enable-based clock gating (alu_enable, mem_enable, regfile_enable)

50% ALU logic power reduction (0.002W → 0.001W)

Secure reconfigurable UART with LFSR encryption

Runtime mode switching: Plaintext ↔ Encrypted

Complete SoC: 127 LUTs, 89 flip-flops

Technologies

Verilog HDL Xilinx Vivado Artix-7 FPGA LFSR

Key Results

50% ALU power reduction

61.3% frequency improvement (143.2 → 231.0 MHz)

87.9% setup slack improvement (3.018 → 5.671 ns)

127 LUTs, 89 FFs (<1% of Artix-7)

Publications

Low Power Optimization Techniques in RISC-V Architecture Using Clock Gating

Status: Under Preparation | Target: IEEE Conference

Low-Power RISC-V SoC with Secure Reconfigurable UART

Status: Under Preparation | Target: IEEE/Springer Conference

Secure Reconfigurable UART

UART with LFSR-based stream cipher encryption. Zero latency, 15 LUTs, 100% accuracy.
Verilog | LFSR | Vivado

Key Features

8-bit LFSR with polynomial x⁸ + x⁶ + x⁵ + x⁴ + 1

Zero latency overhead (XOR is combinational)

Mode switch in 1 clock cycle (20 ns at 50 MHz)

100% accuracy across 4 test cases

15 LUTs, 10 flip-flops per LFSR instance

Technologies

Verilog HDL Xilinx Vivado LFSR

Key Results

15 LUTs, 10 flip-flops per LFSR instance

96.5% area reduction vs AES-128

Zero latency overhead

100% functional accuracy

Publications

Secure Reconfigurable UART with LFSR Encryption

Status: Under Preparation | Target: Springer Conference

SoC-SecureUART

Multi-layer secure RISC-V SoC with PUF, Crypto, TEE, and IOMMU isolation.
Verilog | PUF | AES | Keccak

Key Features

Layer 1: PUF-based Secure Boot (64-bit RO-PUF)

Layer 2: Cryptographic Acceleration (Keccak, DOM-AES)

Layer 3: Trusted Execution Environment (PMP, enclaves)

Layer 4: IOMMU DMA Isolation

3 security modes: Plain, Rolling Code, Challenge-Response

Technologies

Verilog HDL RO-PUF DOM-AES Keccak IOMMU

Key Results

3,654 LUTs (35.1%), 2,138 flip-flops (10.3%)

Max frequency: 83.2 MHz

Total power: 40.2 mW

PUF uniqueness: 47.3%, Reliability: 96.8%

Publications

SoC-SecureUART: Multi-Layer Hardware Security for RISC-V

Status: Under Preparation | Target: IEEE Conference

Portfolio Website

Responsive portfolio showcasing VLSI and web development skills.
HTML | CSS | JavaScript

Key Features

Modern responsive dark theme

Typing animation for roles

Skills with progress bars

Expandable project details

Contact form with validation

Technologies

HTML5 CSS3 JavaScript Boxicons

Key Results

Fully responsive on all devices

Smooth animations and navigation

Interactive project details

Contact Me

Email

kosuru0062@gmail.com

Phone

+91 9398394847

Location

Vizag / Tenali, India

LinkedIn

linkedin.com/in/kosuru-karthik